Automate EDA with AI Assistants
EDA MCP Server lets Claude run Verilog synthesis, simulation, and full RTL-to-GDSII ASIC flows through natural language.
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Why it matters
Integrate AI assistants with your Electronic Design Automation toolchain. Automate Verilog synthesis, simulation, and ASIC flows, enabling AI-driven hardware design.
Outcomes
What it gets done
Synthesize Verilog code using Yosys for FPGA targets.
Simulate Verilog projects with Icarus Verilog.
Execute complete ASIC flows with OpenLane.
View simulation signals with GTKWave and GDSII files with KLayout.
Source
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Capabilities
Tools your agent gets
Synthesize Verilog code using Yosys for FPGA targets (generic, ice40, xilinx)
Simulate Verilog projects using Icarus Verilog with automatic testbench execution
Launch GTKWave to visualize and analyze VCD signal files
Execute complete RTL-to-GDSII ASIC design flow using OpenLane and Docker
Open GDSII files in KLayout for physical design inspection
Read and analyze OpenLane reports for PPA metrics and design quality assessment
Overview
EDA MCP Server
EDA MCP Server gives AI assistants access to Verilog synthesis, simulation, and full RTL-to-GDSII ASIC design flows via Yosys, Icarus Verilog, OpenLane, and KLayout. Use it when an AI assistant needs to synthesize, simulate, or run a full ASIC design flow on a Verilog design.
What it does
EDA MCP Server is a Model Context Protocol server, implementing the MCP4EDA research paper's approach, that gives AI assistants like Claude Desktop and Cursor IDE access to Electronic Design Automation tools. It lets an AI assistant perform Verilog synthesis, simulation, ASIC design flows, and waveform analysis through one unified interface, rather than you running each EDA tool by hand from the command line.
When to use - and when NOT to
Use it when you want an AI assistant to synthesize Verilog for an FPGA target, simulate a design against a testbench, run a complete RTL-to-GDSII ASIC flow, or inspect waveform data, all from a natural-language request such as "Can you synthesize this counter module for an ice40 FPGA?" or "Run the complete ASIC flow for this design with a 10ns clock period." It depends on a real, separately installed EDA toolchain behind it: Yosys for synthesis, Icarus Verilog for simulation, GTKWave for waveforms, and OpenLane plus Docker Desktop and KLayout for the full ASIC flow. It is not a self-contained simulator; it orchestrates these established open-source EDA tools rather than replacing them.
Capabilities
The server covers the full digital design pipeline through its underlying toolchain. Verilog synthesis runs through Yosys for FPGA targets such as generic, ice40, and Xilinx. Verilog simulation runs through Icarus Verilog with automated testbench execution. Waveform viewing launches GTKWave for VCD file visualization and signal analysis. The complete RTL-to-GDSII ASIC design flow runs through OpenLane with Docker, and layout viewing opens the resulting GDSII files in KLayout for physical design inspection. Report analysis reads and interprets OpenLane's reports for power, performance, and area (PPA) metrics and overall design quality. A completed ASIC flow run produces the final GDSII layout, a complete execution log, and timing, area, and power analysis reports, along with intermediate DEF files and netlists.
How to install
Install the underlying EDA tools first: Yosys, via brew install yosys on macOS or apt-get install yosys on Ubuntu/Debian, or the OSS CAD Suite bundle; Icarus Verilog, via brew install icarus-verilog or apt-get install iverilog; GTKWave; Docker Desktop for OpenLane; OpenLane itself, via pip install openlane followed by docker pull efabless/openlane:latest; and KLayout for viewing finished layouts. Then clone and build the MCP server itself and configure it in your MCP client, such as Claude Desktop or Cursor IDE, following the project's Docker Desktop MCP integration or Cursor IDE setup instructions.
Who it's for
Hardware and FPGA/ASIC designers who want an AI assistant to run synthesis, simulation, and full RTL-to-GDSII flows conversationally, instead of driving Yosys, Icarus Verilog, GTKWave, OpenLane, and KLayout separately from the command line.
Source README
EDA Tools MCP Server
Implementation of the paper: MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization
A comprehensive Model Context Protocol (MCP) server that provides Electronic Design Automation (EDA) tools integration for AI assistants like Claude Desktop and Cursor IDE. This server enables AI to perform Verilog synthesis, simulation, ASIC design flows, and waveform analysis through a unified interface.
Demo
https://github.com/user-attachments/assets/65d8027e-7366-49b5-8f11-0430c1d1d3d6
EDA MCP Server demonstration showing Verilog synthesis, simulation, and ASIC design flow
Features
- Verilog Synthesis: Synthesize Verilog code using Yosys for various FPGA targets (generic, ice40, xilinx)
- Verilog Simulation: Simulate designs using Icarus Verilog with automated testbench execution
- Waveform Viewing: Launch GTKWave for VCD file visualization and signal analysis
- ASIC Design Flow: Complete RTL-to-GDSII flow using OpenLane with Docker integration
- Layout Viewing: Open GDSII files in KLayout for physical design inspection
- Report Analysis: Read and analyze OpenLane reports for PPA metrics and design quality assessment
Prerequisites
Before using this MCP server, you need to install the following EDA tools:
1. Yosys (Verilog Synthesis)
macOS (Homebrew):
brew install yosys
Ubuntu/Debian:
sudo apt-get update
sudo apt-get install yosys
From Source:
# Install prerequisites
sudo apt-get install build-essential clang bison flex \
libreadline-dev gawk tcl-dev libffi-dev git \
graphviz xdot pkg-config python3 libboost-system-dev \
libboost-python-dev libboost-filesystem-dev zlib1g-dev
# Clone and build
git clone https://github.com/YosysHQ/yosys.git
cd yosys
make -j$(nproc)
sudo make install
Alternative - OSS CAD Suite (Recommended):
Download the complete toolchain from: https://github.com/YosysHQ/oss-cad-suite-build/releases
2. Icarus Verilog (Simulation)
macOS (Homebrew):
brew install icarus-verilog
Ubuntu/Debian:
sudo apt-get install iverilog
Windows:
Download installer from: https://bleyer.org/icarus/
3. GTKWave (Waveform Viewer)
Direct Downloads (Recommended):
- Windows: Download from SourceForge
- macOS: Download from SourceForge or use Homebrew:
brew install --cask gtkwave - Linux: Download from SourceForge or use package manager:
sudo apt-get install gtkwave
Alternative Installation Methods:
# macOS (Homebrew)
brew install --cask gtkwave
# Ubuntu/Debian
sudo apt-get install gtkwave
# Build from source (all platforms)
git clone https://github.com/gtkwave/gtkwave.git
cd gtkwave
meson setup build && cd build && meson install
4. Docker Desktop (Recommended for OpenLane)
Direct Downloads:
- Windows: Download Docker Desktop for Windows
- macOS: Download Docker Desktop for Mac or
brew install --cask docker - Linux: Download Docker Desktop for Linux
Installation:
- Download and install Docker Desktop from the official website
- Launch Docker Desktop and ensure it's running
- Verify installation:
docker run hello-world
Note: Docker Desktop includes Docker Engine, Docker CLI, and Docker Compose in one package.
5. OpenLane (ASIC Design Flow)
Simple Installation Method (Recommended):
# Install OpenLane via pip
pip install openlane
# Pull the Docker image
docker pull efabless/openlane:latest
# Verify installation
docker run hello-world
Usage Example:
# Create project directory
mkdir -p ~/openlane-projects/my-design
cd ~/openlane-projects/my-design
# Create Verilog file (counter example)
cat > counter.v << 'EOF'
module counter (
input wire clk,
input wire rst,
output reg [7:0] count
);
always @(posedge clk or posedge rst) begin
if (rst)
count <= 8'b0;
else
count <= count + 1;
end
endmodule
EOF
# Create configuration file
cat > config.json << 'EOF'
{
"DESIGN_NAME": "counter",
"VERILOG_FILES": ["counter.v"],
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0
}
EOF
# Run the RTL-to-GDSII flow
python3 -m openlane --dockerized config.json
Key Benefits:
- The
--dockerizedflag handles all tool dependencies automatically via Docker
6. KLayout (Layout Viewer)
Direct Downloads (Recommended):
- Windows: Download KLayout for Windows
- macOS: Download KLayout for macOS or
brew install --cask klayout - Linux: Download KLayout for Linux or
sudo apt install klayout
Alternative Installation:
# macOS (Homebrew)
brew install --cask klayout
# Ubuntu/Debian
sudo apt install klayout
Installation
1. Clone and Build the MCP Server
git clone https://github.com/NellyW8/mcp-EDA
cd mcp-EDA
npm install
npm run build
npx tsc
2. Project Structure
mcp-EDA/
├── src/
│ └── index.ts # Main server code
├── build/
│ └── index.js # Compiled JavaScript
├── package.json
├── tsconfig.json
└── README.md
Configuration
Docker Desktop MCP Integration
This method uses Docker Desktop's built-in MCP extension for the easiest setup experience.
Prerequisites
- Docker Desktop 4.39.0+ installed and running
- Claude Desktop installed
Setup Steps
Install Docker Desktop Extension:
- Launch Docker Desktop
- Go to "Extensions" from the left menu
- Search for "AI Tools" or "Docker MCP Toolkit"
- Install "Labs: AI Tools for Devs" extension
Configure Docker MCP Connection:
- Open the installed "Labs: AI Tools for Devs" extension
- Click the gear icon in the upper right corner
- Select the "MCP Clients" tab
- Click "Connect" for "Claude Desktop" or "Cursor IDE"
This automatically configures Claude Desktop and Cursor IDE with:
{ "mcpServers": { "MCP_DOCKER": { "command": "docker", "args": [ "run", "-i", "--rm", "alpine/socat", "STDIO", "TCP:host.docker.internal:8811" ] } } }
Cursor IDE Setup
Add Your EDA MCP Server:
- Locate your Claude Desktop config file, Settings > Developer > Edit Config:
- macOS:
~/Library/Application Support/Claude/claude_desktop_config.json - Windows:
%APPDATA%\Claude\claude_desktop_config.json
- macOS:
- Add your EDA server to the existing configuration:
{ "mcpServers": { "MCP_DOCKER": { "command": "docker", "args": [ "run", "-i", "--rm", "alpine/socat", "STDIO", "TCP:host.docker.internal:8811" ] }, "eda-mcp": { "command": "node", "args": [ "/absolute/path/to/your/eda-mcp-server/build/index.js" ], "env": { "PATH": "/usr/local/bin:/opt/homebrew/bin:/usr/bin:/bin", "HOME": "/your/home/directory" } } } }- Locate your Claude Desktop config file, Settings > Developer > Edit Config:
Restart Claude Desktop and verify both servers are running in Settings > Developer.
Cursor IDE Setup
Open Cursor Settings:
- Press
Ctrl + Shift + P(Windows/Linux) orCmd + Shift + P(macOS) - Search for "Cursor Settings"
- Navigate to "MCP" in the sidebar
- Press
Add MCP Server:
Click "Add new MCP server" and configure:{ "mcpServers": { "MCP_DOCKER": { "command": "docker", "args": [ "run", "-i", "--rm", "alpine/socat", "STDIO", "TCP:host.docker.internal:8811" ] }, "eda-mcp": { "command": "node", "args": [ "/absolute/path/to/your/eda-mcp-server/build/index.js" ], "env": { "PATH": "/usr/local/bin:/opt/homebrew/bin:/usr/bin:/bin", "HOME": "/your/home/directory" } } } }Enable MCP Tools:
- Go to Cursor Settings → MCP
- Enable the "eda-mcp" server
- You should see the server status change to "Connected"
Usage Examples
1. Verilog Synthesis
Ask Claude: "Can you synthesize this counter module for an ice40 FPGA?"
module counter(
input clk,
input rst,
output [7:0] count
);
reg [7:0] count_reg;
assign count = count_reg;
always @(posedge clk or posedge rst) begin
if (rst)
count_reg <= 8'b0;
else
count_reg <= count_reg + 1;
end
endmodule
2. Verilog Simulation
Ask Claude: "Please simulate this adder with a testbench"
// Design
module adder(
input [3:0] a,
input [3:0] b,
output [4:0] sum
);
assign sum = a + b;
endmodule
// Testbench will be generated automatically or you can provide one
3. ASIC Design Flow
Ask Claude: "Run the complete ASIC flow for this design with a 10ns clock period"
module simple_cpu(
input clk,
input rst,
input [7:0] data_in,
output [7:0] data_out
);
// Your RTL design here
endmodule
What you get after completion:
runs/RUN_*/final/gds/design.gds- Final GDSII layoutruns/RUN_*/openlane.log- Complete execution logruns/RUN_*/reports/- Timing, area, power analysis reports- All intermediate results (DEF files, netlists, etc.)
4. Waveform Analysis
Ask Claude: "View the waveforms from the simulation with project ID: abc123"
Troubleshooting
Common Issues
MCP Server Not Detected:
- Verify the absolute path in configuration
- Check that Node.js is installed and accessible
- Restart Claude Desktop/Cursor after configuration changes
Docker Permission Errors:
sudo groupadd docker sudo usermod -aG docker $USER sudo rebootTool Not Found Errors:
- Verify tools are installed:
yosys --version,iverilog -V,gtkwave --version - Check PATH environment variable in MCP configuration
- On macOS, ensure Homebrew paths are included:
/opt/homebrew/bin
- Verify tools are installed:
OpenLane Timeout:
- The server has a 10-minute timeout for OpenLane flows
- For complex designs, consider simplifying or running multiple iterations
GTKWave/KLayout GUI Issues:
- On macOS: GTKWave/KLayout may need manual approval in Security & Privacy settings
- On Linux: Ensure X11 forwarding is working if using remote systems
- On Windows: Ensure GUI applications can launch from command line
Debugging
Check MCP Server Logs:
- Claude Desktop:
~/Library/Logs/Claude/mcp*.log(macOS) - Cursor: Check the MCP settings panel for error messages
- Claude Desktop:
Test Tools Manually:
yosys -help iverilog -help docker run hello-world gtkwave --version klayout -vVerify Node.js Environment:
node --version npm --version
Cite
@misc{wang2025mcp4edallmpoweredmodelcontext,
title={MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization},
author={Yiting Wang and Wanghao Ye and Yexiao He and Yiran Chen and Gang Qu and Ang Li},
year={2025},
eprint={2507.19570},
archivePrefix={arXiv},
primaryClass={cs.AR},
url={https://arxiv.org/abs/2507.19570},
}
FAQ
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