Generate ARM Cortex Firmware and Drivers

Delivers complete, compilable firmware and driver modules for ARM Cortex-M microcontrollers - Teensy 4.x (i.MX RT1062, Cortex-M7), STM32 F4/F7/H7 (Cortex-M4/M7), nRF52 (Cortex-M4, BLE), and SAMD (Cortex-M0+/M4) - covering peripheral drivers (I2C, SPI, UART, ADC, DAC, PWM, USB), software architecture (HAL layering, interrupt safety, memory management), concurrency (ISRs, ring buffers, event queues, FreeRTOS/Zephyr integration), and performance (DMA transfers, cache effects, timing, memory barriers), always prioritizing correctness first and optimizing only after profiling.

Cortex-M7 platforms specifically (Teensy 4.x, STM32 F7/H7) get dedicated safety-critical guidance because their weakly-ordered memory can reorder register reads and writes: register access needs a data memory barrier before and after reads and a data synchronization barrier after writes, wrapped in helper functions in C/C++ or Rust's cortex_m barrier intrinsics, since the telltale symptom - works with debug prints, fails without them - is a barrier bug in disguise. DMA buffers on these same cache-equipped chips must be 32-byte aligned, the M7's cache line size, and sized to a multiple of 32 bytes, or a cache invalidate during DMA corrupts adjacent memory; the preferred fix is placing buffers in non-cacheable DTCM/SRAM rather than relying on manual cache flush and invalidate calls as a last resort. A separate hard rule covers write-1-to-clear status registers common on i.MX RT and STM32:

uint32_t status = mmio_read(&USB1_USBSTS);
mmio_write(&USB1_USBSTS, status);  // Write bits back to clear them

writing the read-back status value clears the set bits, while the intuitive status &= ~bit does nothing at all on a W1C register.

Platform-specific gotchas are named directly: Teensy 4.x's FlexSPI is dedicated to Flash/PSRAM only and its emulated EEPROM tolerates writes below 10Hz; STM32 F7/H7 has fixed DMA stream and channel assignments; nRF52's SAADC needs calibration after power-on and GPIOTE is limited to 8 channels; SAMD's SERCOM needs careful pin muxing and M0+ variants have limited DMA. Modern Rust guidance is explicit that static mut is undefined behavior and shared state belongs in an atomic type or a mutex-protected cell accessed through a critical-section token instead. NVIC interrupt priority guidance covers the platform-dependent priority level count, from 2-4 on M0/M0+ up to 256 on M3/M4/M7, the lower-number-means-higher-priority convention, and reserving the highest priorities for time-critical DMA and timers. Critical sections favor masking only lower-priority interrupts via BASEPRI over disabling all interrupts via PRIMASK, and must stay short, microseconds rather than milliseconds.

Use it when developing firmware or drivers for Teensy, STM32, nRF52, or SAMD Cortex-M microcontrollers, or debugging platform-specific issues like intermittent hardware failures, hardfaults, or memory corruption. Hardfault debugging starts from the most common causes: unaligned memory access, especially on M0/M0+, null pointer dereferences, and stack overflow. It is not the right tool for tasks unrelated to embedded ARM Cortex-M development.

Takes a peripheral driver, concurrency, or platform-safety requirement for a specific Cortex-M target; produces complete driver code with initialization, ISR, and example usage, annotated with register-level and buffer-structure explanations plus documented tradeoffs.

Embedded engineers writing firmware or drivers for Teensy, STM32, nRF52, or SAMD Cortex-M platforms who need correct memory-barrier, cache-coherency, and interrupt-safety patterns rather than code that happens to work until a compiler optimization or timing change breaks it.